Knowledge Goes Free - Learn About VLSI

A career in VLSI is very challenging. Not only because this career is too dynamic, but also its very research and knowledge intensive. As Moore's law predict that the integration of devices on a chip area will double every 18 months (note that he had initially predicted it to be 2 years i.e. around 33% less dynamic) it means a lot to a career in VLSI. It tells how quickly the technology changes and how we have to remain updated with the cutting edge technology.
This means the knowledge in this field is not only inevitable but also should be accessible at the right time. Especially, the knowledge related to pioneering technology and on-going research (generally available at industry research labs or classrooms of premiere universities) should get to the market quickly for techies to access and implement it. This blog has an aim to spread awareness and knowledge for the same cause and with this post we are a step ahead.
There are some open course ware thats free for every one to access. So, this knowledge is free and its on us to make proper use of it. Moreover, they are from some of the best institute around the world whose link is provided here:
1. Free video lectures and animations on all subjects Huge Collection. Text materials and videos on all Engineering and Medical Sciences.
2. Joint venture by IIT's and IISc
3. MIT Open Course Text materials, video lectures on all subjects
4. MIT world Video lectures
5. MIT lecture Browser browse video lectures on all topics
6. World Lecture Hall you can find any course here, where ever it is

7. UC Berkeley Course Above link contains webcasts of courses taught at University of California Berkeley. They are categorized under various semesters(top right corner).
Other Useful Search Engines:
1. Google Book Search Search the all books.

2. Google Code Search searches public source code

3. Google Scholar Search searches all the Scholar papers.

4. Educational Special Search Engine searches all sites for e-books, study materials, video lectures, animations, including Google videos, Yahoo videos, you tube, Google code search, Scholar, Book search.

There are some other links that relates to other different areas too. However, its not published here as its out of context. Please mention it in the comments if you need any of those links. So, please make use of these free knowledge sites and make proper use of it. Happy browsing.

Beyond immersion lithography

- Source: EDN Asia Newsletter, By: Kirtimaya Varma, Date: 01, Oct, 2008

While designers move toward 32nm, two reports from IMEC should be of special interest for them. The first is the end of the road for immersion lithography. This is rather disappointing, because high-index immersion lithography using non-water fluids between the optical lens and the wafer was designed to push 193nm immersion lithography toward the 32nm node. Its elimination from the race for the next-generation lithography tools has not come suddenly. Designers had found that in deep nanometrics immersion lithography was behind the roadmap. But now it is confirmed that this lithography has reached its limits.

LITHOGRAPHY OPTIONS: The two lithography options being developed for 32nm and possibly beyond are double patterning and EUV. EUV technology is still years away and is expected to mature only in the middle of the next decade. This leaves double patterning to bridge the gap between immersion and EUV lithographies. Most designers agree that double patterning will be the best option for the 32nm half pitch during early next decade, and some hope that EUV will take over at 22nm half pitch. However, there is no consensus on which of the several double patterning approaches using the existing 193nm immersion toolset will prevail. For one thing, all the present double patterning methods entail huge extra costs because of extra process steps involved. IMEC is conducting a study on various double patterning methods with a view to assess the feasibility and cost-effectiveness of various processes and to validate the most promising ones in terms of cost, implementation, and process controllability, and is developing alternate process flows that reduces the cost-of-ownership by eliminating the intermediate etch step and replacing it with a process step in the litho track. The method IMEC has used to eliminate the extra etch step is through freezing the resist after the first exposure. The freezing material, developed by JSR Corporation and compatible with the lithography hardware, prevents the resist from expanding or contracting, so that when the second resist layer is added, the two do not interact. Besides, the freezing material changes the properties of the first resist layer to make it non-soluble in the second resist layer solvent. IMEC is developing this technique in collaboration with resist supplier and is working on improvements of the process conditions, process window, line-edge roughness, overlay, defectivity, and etch performance. With EUV lithography still far away, it is not known how will EUV impact the cost of a design? Today no known EUV radiation source produces sufficient power. With costs going through the roof, some designers are wary of being too optimistic about EUV and believe that double patterning will not stop at 32nm and will extend to nodes beyond. In this connection it is important to note that IMEC has completed the site acceptance tests for ASMLs Alpha-Demo EUV tool that has successfully patterned the contact level of a 32nm SRAM cell using EUV.

DIELECTRIC BREAKTHROUGH: Yet another important announcement IMEC made is its progress on simplified high-K/metal gate process for 32nm node. K has been a matter of concern ever since designs reached 90nm. It is too early to say whether a final solution has emerged, but IMEC reports improved performance for its planar CMOS using hafnium-based high-K dielectrics and tantalum-based metal gates for the 32nm CMOS node. IMEC has simplified its high-K/metal gate process by decreasing the number of process steps from 15 to 9.

IMEC also claims to have simplified the process complexity from dual-metal dual-dielectric to single-metal dual-dielectric by using soft-mask processes and wet removal chemistry. The process reduces the complexity by 40 percent or 6 steps compared to dual-metal dual-dielectric, while allowing simpler gate-etch profile control and offering better prospects for scaling. IMEC works with its core 32nm CMOS partners, including Infineon, Qimonda, Intel, Micron, NXP, Panasonic, Samsung, STMicro, TI, TSMC , Elpida and Hynix.

Link: http://www.ednasia.com/article-21907-Asia.html

Sun-tracking device wins student prize

- Source: IEEE Students, October Newsletter, By: David Chandler, MIT News Office, Date: September 19, 2008

A team of three students who designed a system that could allow solar power panels to track the sun without motors or control systems won top honors Thursday -- and a check for $10,000 -- in the finals of a competition aimed at developing innovative energy technologies.
This was the second annual MADMEC -- which stands for Making And Designing Materials Engineering Contest -- and it offered students six categories of engineering challenges related to producing innovative solutions for energy-related problems in the developing world. The contest is co-sponsored by MIT's Department of Materials Science and Engineering (DMSE) and by corporate sponsors Dow Chemical, Saint Gobain and General Motors.
The competition began last spring, and all four of the teams that made it to the finals won prizes, ranging from the $10,000 top award to $1,000 for the fourth-place finishers.
The winning team, called Heliotrope, chose to imitate the way plants track the sun across the sky, by using the difference in temperature between shaded and sunny areas to change the properties of the material supporting solar photovoltaic cells. The system, once built, is completely passive, requiring no power source or electronics to control the movement. Solar cells that track the angle of the sun can be 38 percent more efficient at generating power than those that are mounted in a fixed position, explained team member George Whitfield, a graduate student in DMSE.
The team explored several different variations of the proposed system, using various materials including polymers and bimetallic strips. The system that shows the most promise, they said, mounts solar panels at the top of a curved arch made of a pair of metals such as aluminum and steel, which should be durable enough to withstand the elements with little or no maintenance.
"We wanted to show this concept in action," Whitfield explained as he demonstrated a scale model of the arch by shining a spotlight to warm up one side and cause the arch to bend, tilting the solar panel toward the light. "Our prototypes are cheaper than existing systems" for tracking the sun, he said, and could be built from materials that are readily available in developing nations.
The second-place winner was a team that worked on a way to make inexpensive coatings for windows that would block infrared light, thus allowing daylight through while blocking the sun's heat to reduce the need for air conditioning. Third place went for simple wind generators that could be placed alongside a road to produce electricity from the movement of passing cars. And the fourth prize went to a simple attachment for a bicycle that could allow it to generate electricity to charge batteries, such as those used in the One Laptop Per Child computers.
"I was very impressed with all the entries," said Ned Thomas, DMSE head and Morris Cohen Professor of Materials Science and Engineering. The department will definitely plan on holding another MADMEC competition starting next spring, he said.

Link: http://web.mit.edu/newsoffice/2008/madmec-0919.html

Novaled Achieves CMOS Logic Technology Breakthrough

- Source: IEEE Circuits, September Newsletter

Making n- and p-type organic thin-film transistors from the same organic semiconductor material could benefit lighting and display technology.
Organic CMOS transistors are attractive for applications where classical silicon-based systems are too expensive. To date most developments in organic CMOS devices are based on pentacene, which usually allows for p-type transistors only, so organic thin-film transistors (OTFTs) have had to use two different organic semiconductors as active layers in order to show n- and p-type behaviour. Novaled has now demonstrated that both n-type and p-type OTFTs can be made from only one active material.
"It is well known that using doped transport layers in OLEDs reduces the driving voltage, increases lifetime and boosts power efficiency," Anke Lemke of Novaled told optics.org. "Now we have shown that introducing redox dopants into OTFTs can change the type of majority carrier. The performance of p-type pentacene OTFTs can be improved by using p-dopants, while introducing n-dopants can change the OTFT from p- to n-type."
This enables the use of "CMOS logic" in organic electronics applications, circuit designs based on n- and p-type transistors featuring low static power dissipation compared to logic circuits using only one type of transistor. Both the performance and the manufacturability of OTFT circuits could be improved by this breakthrough.
"The complementary logic-OTFTs could be used in the lighting and display markets, but also in other sectors such as organic RFIDs," said Lemke. "In the display field, possible applications are backplane driving circuits for active matrix displays."
Introducing dopants into existing organic transistor technologies seems straightforward, but Lemke pointed out that the processing compatibility appears to be even more important with OTFTs than with OLEDs. "Our results so far are proof-of-concept, and we are now starting to transfer our approach to industrial processes. The number of commercially available organic electronic devices is still small, but as they become more widely available we are optimistic that our technology can be introduced commercially in the medium-term."
• Novaled and Vitex have announced a co-operation on OLED thin-film encapsulation, intending to combine the advantages of the Barix thin-film technology developed by Vitex and Novaled's doping technology and produce ultrathin highly efficient OLEDs.
"We intend to integrate Vitex barrier technology into Novaled's OLED prototypes and development programme, and offer a more complete set of OLED component expertise," commented Novaled's Lemke.
Novaled intends to begin offering thin OLED lighting prototype products incorporating the combined technology to lighting companies starting in 2009.

Creating a purer breed of semiconductors

- Source: IEEE Circuits, September Newsletter, By: Sylvie Barak, The Inquirer

FANS OF ELECTRON mobility research rejoice! Boffins at Germany’s Physikalisch Technische Bundesanstalt (PTB) have come up with a brand spanking new high-vacuum semiconductor crystal generation process which purports to produce crystals five times purer than all previous known epitaxy systems.
PTB’s new system apparently relies on an innovative molecular beam epitaxy system, with GaAs (gallium-arsenide) and AlGaAs (aluminum-gallium-arsenide) semiconductor heterostructures forming a base. These are then evaporated in a vacuum and laid down in atomic layers, only a few nanometers thin. These then form an electron layer within the crystals, called a two-dimensional electron gas.
Mobility of electrons depends quite significantly on lowering the amount of impurities, so, to mop up the nasty stuff, the boffins have added special cooling panels to suck up any unwanted waste.
To generate the crystals themselves, a special ultrahigh vacuum is used. At 15 orders of magnitude beneath standard atmospheric pressure, you could say, it sucks. Big time. It is also, by no means, an easy feat and requires multiple stages of vacuum creation, starting with partial vacuums and moving up.
Once the vacuum has been formed, the molecular-beam epitaxy gets going, allowing the incredibly pure crystals to form using the aforementioned layering system.
All this, ultimately, leads to a much purer form of semiconductor, which is good news for Chipzilla and Moore’s Law advocates, as well as to those looking into things like quantum Hall resistance metrology and new thinking on electrical current as a function of frequency and electron charge.
Exciting stuff indeed.

HP Plans to Incorporate Memristors into Electronics Mainstream

- Source: IEEE Circuits, September Newsletter, By: R. Colin, EETimes

The transistor was invented in 1925 but lay dormant until finding a corporate champion in Bell Labs during the 1950s. Now another groundbreaking electronic circuit may be poised for the same kind of success after languishing as an academic curiosity for more than three decades.
Hewlett-Packard Labs is attempting to catapult the memristor, the fourth passive circuit element after resistors, capacitors and inductors, into the electronics mainstream. Invented in 1971, this "memory resistor" represents a potential revolution in electronic-circuit theory akin to the invention of the transistor -- and perhaps its time has finally come. But as with that earlier device, it will take a killer application to get it off the ground.
Where the hearing aid played that role for the transistor, Hewlett-Packard Labs (Palo Alto, Calif.) hopes resistive random-access memories (RRAMs) will open the floodgates for the memristor. HP Labs is promising prototypes of these ultradense memory cells next year.
"I'd say memristors give HP a chance to become the dominant leader in memory technology in 10 years," said Martin Reynolds, vice president of Gartner Inc. (Stamford, Conn.). "We have seen HP reinvent itself a number of times in the past, and this is a technology that could really drive that kind of change in the company again."
However, the clock is ticking. Last year, HP's crossbar switches -- the building blocks of a new memory type the company is developing -- were more than 20 times denser than flash memories, giving HP breathing room to perfect its RRAMs. But in less than a year, flash memories have upped their density fourfold to eightfold by going to 2- and 3-bit-per-cell configurations, respectively.
That unforeseen leap has narrowed HP's advantage. RRAMs now claim just three times the density of flash, evoking memories of the same scenario that has doomed other next-generation memory technologies.
"When HP started work on the crossbar several years ago, they were 40 or 50 times denser than flash," said Reynolds. "But now they are only about three times denser than flash." To stay ahead, he said, HP will have to figure out how to boost the memristor's current density of 100 Gbits/cm2 "to a terabit in a square centimeter."

Gordon Moore to Receive IEEE Medal of Honor

- Source: IEEE Circuit, September Newsletter, By: Staff -- Semiconductor International

Known widely for his prediction of the doubling of transistors on a chip, Gordon E. Moore, co-founder and chairman of the board, emeritus, at Intel Corp., has won several prominent awards over the years. The latest comes from the Institute of Electrical and Electronics Engineers (IEEE, Piscataway, N.J.), which is giving Moore the IEEE Medal of Honor for his contributions to the advancement of semiconductor technology, both as an engineer and entrepreneur.
The award, sponsored by the IEEE Foundation, recognizes Moore for pioneering technical roles in IC processing and leadership in the development of MOS memory, the microprocessor computer and the semiconductor industry. The IEEE Medal of Honor will be presented to Moore Sept. 20 at the IEEE Honors Ceremony in Quebec City, Canada.
Moore’s contributions, both fundamental and practical, defined semiconductor technology and helped drive the advancement of the global electronics industry. In 1965, he introduced a theory that has become a guiding principle for the semiconductor industry. Moore predicted that the number of transistors able to be placed on a silicon chip would double each year for 10 years. During that 10-year period, the number of transistors on a single chip increased from 64 to 64,000, proving his theory correct. In 1975, he updated this prediction to stipulate that the complexity of chips would double every two years. These predictions, known in the industry as Moore’s Law, served as a roadmap for the development and advancement of the global semiconductor industry. This exponential increase in chip density, coupled with significant reductions in cost, enabled the widespread use of integrated electronics, which led to the emergence of many prominent segments of the electronics industry, including personal computing, mobile communications and consumer electronics.
In addition to his technical work, Moore achieved prominence for his involvement in the establishment of two pioneering semiconductor companies: Fairchild Semiconductor, which produced the first practical ICs in 1957, and Intel Corp., which developed a number of products based on LSI technology, including the world’s first microprocessor in 1968. Intel is currently the world’s largest semiconductor company.
Along with his team at Fairchild Semiconductor, Moore is credited with the development of the Silicon Valley Management Style, which treats the corporation as an extension of the scientific laboratory, overlooking each employee’s place on the organizational chart and emphasizing the contribution of creativity and knowledge from every level.
Moore has authored more than 80 papers on semiconductor technology and holds multiple patents. He has received numerous awards and honors, including the IEEE Frederik Phillips Award, IEEE Founders Medal, the National Medal of Technology, the Presidential Medal of Freedom, and the EE Times ACE Awards Lifetime Achievement Award.
An IEEE Life Fellow, Moore is a member of the National Academy of Engineering and a Fellow of the Royal Society of Engineers. Moore holds a bachelor’s degree in chemistry from the University of California, Berkeley, and a doctorate in chemistry and physics from the California Institute of Technology. He serves as a director of several companies and is active in several professional and philanthropic organizations.

New tech increases yields and performance of organic circuits

-Source: IEEE Circuits newsletter, Provided: Trendwatch, By Rick C. Hodgin, Dated: Friday, September 05, 2008

Chicago (IL) - Researchers from the Center for Neutron Research at National Institute for Standards and Technology (NIST), and Seoul National University (SNU), have cooperatively developed a way to tweak the a crucial design aspect for printed organic-based semiconductor circuits. The redesign not only makes them easier to manufacture, but also increases yield and will eventually lead to better performing organic circuits (relative to silicon).

Organic semiconductors are a very hot topic for future low-cost, high-volume applications. If the researchers can work out some of the performance limiting factors, flexible displays like rollable paper would be much easier to produce, as well as many devices which integrate circuitry directly into packaging and products in a cost-effective manner (vis-a-vis Minority Report). This becomes possible because of the way organic circuits are created.Created via ink-jetUnlike conventional semiconductors, which require complex and expensive vacuum as well as high heat and laser processes to manufacture, organic semiconductors are basically sprayed onto a thin film with a type of ink-jet printer. Polymer chemicals are deposited which quickly form into the electrical circuits. Some polymers are used for insulators, others for leads, and it's a 3D stacking effect which makes it all work.The new research has developed a way to move the gate from the top to the bottom, allowing for better molecular materials deposition and higher yields. These improvements add up to an easier-to-manufacture more-likely-to-work circuit and should allow researchers now to focus on performance and stability issues rather than simple design problems. The result: Organic based products could be brought to mass markets in a more timely manner.

Conclusion: The future for organic-based semiconductors will likely be extremely wide. Whereas we will most always turn to more complex forms like silicon- and germanium-based semiconductors for the highest-end performance, when it comes to low-cost manufacturing for "adequate" performance, there are few solutions available which promise as much as organic-based processes.

India, Vietnam Lead Asia's Chip Growth

- Source: IEEE Circuit, September Newsletter, Provided: ZDNet Asia

India is tipped to be the world's fastest growing semiconductor market, with a compound annual growth rate (CAGR) of 19.2 percent between 2007 and 2012, Phillip Koh, Gartner's research vice president for semiconductors in the Asia-Pacific region, said Tuesday at the company's 14th annual semiconductors roadshow here. This means that globally, the Indian market has the highest increase in semiconductors required in devices.
Another fast-growing segment was what Gartner termed as "other Asia-Pacific" markets, which include Southeast Asian nations such as Indonesia, the Philippines, Thailand and Vietnam. Among this group, Vietnam scored the highest CAGR at 46 percent.
Separately, in a statement Monday, Gartner said that the Asia-Pacific market will grow 6.4 percent this year to reach US$160 billion. The analyst house also forecast the regional market to generate a revenue of US$203 billion by 2012.
Koh on Tuesday singled out growing domestic demand for electronic equipment and a supportive investment climate, as drivers for the strong forecast for India and Vietnam. According to him, the Indian semiconductor market is expected to reach US$9.8 billion in 2012, more than double that of US$4.1 billion in 2007, while Vietnam's semiconductor market, added Koh, will be worth US$6.6 billion in 2012.
Over in India, the government has initiated investment policy changes to encourage companies to set up manufacturing presence in the country, noted Koh. It also has growing chip design competencies, accounting for nearly 25 percent of global semiconductor design services revenues for 2008.
Similarly, Vietnam has enjoyed "a lot of investment" within the last two years. The government has also provided much support to drive investment, he said. However, to be able to attract more investors and semiconductor players, the country needs to improve on various aspects of infrastructure such as transportation, as well as intellectual property protection.
"We expect that India is going to drive semiconductor growth [for the region] over the next one to three years; emerging markets like Vietnam will [be a significant contributor] over the longer term," noted Koh.
By 2012, India will contribute 5 percent of the region's semiconductor revenues, up from 3 percent in 2007, while Southeast Asian markets will contribute the majority of the 13 percent forecast for the Asia-Pacific region. China, however, will continue its lion's share of the regional market at 62 percent, up from 59 percent last year.