Air-gaps in Copper Interconnects for Logic

Reference: https://www.linkedin.com/profile/view?id=16600352&trk=nav_responsive_tab_profile

The good people at ChipWorks have released some of the first public data on Intel’s new 14nm-node process, and the results indicate that materials limitations in on-chip electrical interconnects are adding costs. Additional levels of metal have been added, and complex “air-gap” structures have been added to the dielectric stack. Flash memory chips have already used air-gaps, and IBM has already used a subtractive variant of air-gaps with >10 levels of metal for microprocessor manufacturing, but this is the first known use of additive air-gaps for logic after Intel announced that a fully-integrated process was ready for 22nm-node chips.

Mark Bohr of Intel famously published data in 1995 (DOI:  10.1109/IEDM.1995.499187) on the inherent circuit speed limitations of interconnects, showing proportionality to the resistance (R) of the metal lines multiplied by the capacitance (C) of the dielectric insulation around the metal (Fig.1). The RC product thus should be minimized for maximum circuit speed, but the materials used for both the metal and the dielectric insulation around metal lines are at limits of affordability in manufacturing.

There are no materials that super-conduct electricity at room temperature, and only expensive and room-sized supercomputers and telecommunications base-stations can afford to use the liquid-nitrogen cooling that is needed for known superconductors to function. Carbon Nano-Tubes (CNT) and 2D atomic-layers of carbon in the form of graphene can conduct ballistically, but integration costs and electrical contact resistances limit use. Copper metal remains as the best electrical conductor for on-chip interconnects, yet as horizontal lines and vertical vias continue to shrink in cross-sectional area the current density has reached the limit of reliability. The result is the increase in the number of metal layers to 13 for 14nm-node Intel microprocessors, while IBM used 15 layers for 22nm-node Power8 chips.
Low-k Dielectrics and Pore Sizes
The dielectric constant (“k”) of silicon oxide is ~4, and ~3.5 with the addition of fluorine to the oxide (SiOF). Carbon-Doped Oxide (CDO or SiOC or SiOC:H) with k~3.0 has been integrated well into interconnect stacks. Some polymers can provide k values in the 2.0-2.7, but they cannot be integrated into most interconnects due to lack of mechanical strength, chemical resistance, and overall stability. Air has k=1, and there have been specialized chips made using metal wires floating in air, but lack of physical structure results in poor manufacturing yield and weak reliability.
A clever compromise is to use both SiOC with k~3 and air with k~1 in a stack, which results in an integrated k value weighted by the percent of the volume taken up by each phase. Porous Low-k (PLK) with 10% porosity allows for an integrated k of ~2.7 for modest improvement, but increasing porosity to just 20% for k~2.4 results in connected random pores that reduce reliability. To reliably integrate 20-30% air into SiOC, the pores cannot be random but must be engineered as discrete gaps in the structure.
In 2007, IBM announced that it would engineer air-gaps in microprocessors, but the company claimed to be using an extremely complex process for integration involving a self-assembled thin-film mask to anisotropically etch out holes between lines and then further isotropic etching to form elongated pores. Though relatively complex and expensive, this process allows for the use of any 2D layout for lines in a given metal layer.
Additive Air-gap Process-Design Integration
For fab lines that are still working with aluminum metal and additive dielectrics, air-gaps are a defect that occurs with imperfect dielectric fill. When not planned as part of the design, air-gaps formed in a lower-layer can be exposed to etchants during subsequent processing resulting in metal shorts or opens. However, Figure 2 shows that it is possible to engineer air-gaps by Chemical-Vapor Deposition (CVD) of dielectric material into line-space structures with proper process control and design layout restrictions. Twenty years ago, this editor worked for an OEM on CVD processes for dielectric fill, and the process can be tuned to be highly repeatable and relatively low-cost if a critical masking step can be avoided. In 1998, Shieh et al. from Stanford (Shieh, Saraswat & McVittie. IEEE Electron Dev. Lett., January 1998) showed proof-of-concept for this approach to lower k values.

Figure 2: CVD can be easily tuned to initially coat sidewalls (top), then pinch-off (middle), and finally form a closed pore (bottom) during one step. (Source: Ed Korczynski)

Four years ago at IEDM 2010, Intel presented details of how to engineer air-gaps using CVD. As this editor wrote at that time in an extensive analysis:
The lithographic masking step is needed for two reliability reasons. First, by excluding air-gap formation in areas near next-layer vias, alignment between layers can be more easily done. Second, wide spaces are excluded where the final non-conformal CVD step wouldn’t automatically pinch-off to close the gaps; leaving full SiOC(H) in wider spaces also helps with mechanical strength. The next layer is patterned with a conventional dual-damascene flow, with the option to add air-gaps.
Now we know that Intel kept air-gaps on the metaphorical shelf by skipping use at the 22nm-node. The 2014 IEDM paper from Intel will discuss details of 14nm-node air-gaps:   two levels at 80nm and 160nm minimum pitches, yielding a 17% reduction in capacitance delays.
This process requires regularly spaced 1D line arrays as a design constraint, which may also be part of the reason for additional metal layers to allow for 2D connections through vias. Due to lithography resolution advantages with 1D “gridded” layouts, other logic fabs may soon run 1D designs at which point additive air-gaps like that used by Intel will provide a relatively easy boost to IC speeds.
Tags: air gap, ChipWorks, CNT, Copper, Cu, CVD, graphene, IBM, IC, IEDM, integration, Intel, interconnect, logic, low-k, manufacturing, materials, node, PKL, porosity, process, RC, Semiconductor, SiOC, SiOCH, SST News

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Scope of VLSI design and Courses Available at UMN - Part 1

This was my post for my juniors:

VLSI is the worst thing ever happened to me, joked one of my batchmate after taking EE5323 at the semester end. I got a mini-heart attack cause it was best thing ever for me (and she was a girl... there vlsi lost another girl for it's aspirants). So, hope this document inspires or warns future student.

Aim: to understand scope of VLSI and the courses offered at UMN

To be used: On a bright, lazy morning cause the doc will be lengthier (have center fresh chewing gum, if you find VLSI boring :P) Skip to the last part of course, if you are too bored :)

So, let's understand the prospect of VLSI with a VLSI centric world and how the courses here cater to those demands (VLSI says sorry to other EE dept ppl for it's selfishness here :P)

There are two types of jobs: VLSI design and supporting jobs. So here is a typical chip life cycle

There are product architects from different VLSI application field (DSP, communication, wireless, etc). They define the product (IC) at the top level. They need to have a basic understanding of system, computer architecture, not much on circuits or devices though. Once the architecture is finalized, the chip description is being coded at the top level through HDLs (Hardware Description Langauge like Verilog, System Verilog, VHDL) this is called coding and RTL design. These are done at logic level or gate level. So, these engineers need to know basic digital logic design, systems and circuits apart from HDLs; not much devices (electrical aspects) though. Since this phase take long time, a parallel team of programmers write the system model in language called System C and test those modules. These testing can be done in different language for the functionality that the architects intend to get out of the chip. This is testing and the engineer needs to know same thing as RTL design engineers. The end product here is a transistor level code of IC called netlist. The phase from architecture to netlist is called front-end. This phase also contains phases like DFT (design-for-test), STA (Static Timing Analysis), RTL testing, etc.

The netlist code is handed over to back-end or physical designer. Picture this, a software is the final phase of realization, but for hardware code to be realizable - it needs to be manufactured on a physical media (Silicon wafer mainly). The netlist is taken and realized in terms of transistor schematics. This is called circuit design. They check electrical aspects (ac and dc analysis - timing, power, noise). Then this is drawn on a virtual silicon wafer through software tools. This is called layout. The final product is a GDSII, which contains the layout information. These engineers needs to know circuits, logic design, HDLs (they deal with it when taking it from front-end), system, device and fabrication. These are the main guys, who extensively deal with every kind of electrical aspects of chip. (With so much appreciation towards this field, you must have known i am a physical designer)

Both the front-end and back-end is supported by huge computing resources (EDA domain - Electronic Design Automation). These are the VLSI automation tools that support these design engineers to work better and faster in the most advanced technology. They need to know more computers than electrical aspect. Algorithm, C/C++ language, digital logics, computer architecture, system/circuit concepts are some of the desired quality. They also need to support their tool. These are one of the top paid guys in the industry, but work profile is not as satisfactory as designing (my opinion and experience - they can be disturbed at night 2am also and poor guys can't complain too)

The GDSII is sent to fabrication units to be fabricated into chips. The fabrication people need to know devices and VLSI technology (fabrication, semiconductor physics, mechanical engineering, etc). There are other sets of engineers, who decide about chip packaging, wiring and maintenance. These guys need to know materials and electrical aspects (mostly power). According to system type, there are engineers like digital engineer (most of the cicuits are digital), analog engineer (can't exist without digital and vice versa), RF/wireless (mostly part of analog), optics (you know it), power electronics (high voltage devices, i guess- correct me here), etc. And of course how can we forget the researchers - Nano/Micro electronics/technology guys. These are the guys, who find new devices and technology to keep advancing the technology day by day. The advanced domain is more of a research topic with very few commercial usage, because most of technology innovation is done by fab people. Although in recent years, discovery of nanotubes and new means of representing digital logics have infuses funds into the research. These guys needs to know solid state, materials, semiconductor physics, quantum physics, microfab, etc.

So, here is a summary of the scopes:

Architects - develop chip architecture

Front-end engineer - design, develops and test HDL implementation of chip

Back-end engineer - design, develops and verifies transistor and layout implementation of IC

Automation engineer - develop and support flows and tools for designers

Fabrication engineer - manufacture and tests physical IC

Digital engineer - Most public at UMN, friendly, smart and handsome

Analog engineer - conspire with Professor Harjani and make life of digital aspirants hell

RF/Wireless - Analog students who have no other courses left to take

optics - most american, Iranian and international students in those courses at UMN

power electronics - heavily funded and super-rich guys in UMN

Nano-electronics - The gen-next (same public as optics)

Oh shit... it's too huge - let's publish it as a part 1 doc and have dinner... birthday party to attend at midnight too... Courses info coming next... Any discrepancy, please let me know and correct it here...

FAQ:

Q: .can u please comment on the role of analog/microelectronics engineers in the above design process u have explained ?..and also elaborate on how analog design students conspire with prof harjani :p?A: Microelectronics as it names suggest is electronics at the micron range - so VLSI dealing with electronics of micron range devices or ckts is called microelectronics (though most advanced nodes are at nano level now). Guys here learn devices, ckts and systems. Then they chose their domain - ckt design (mainly), Layout or fabrication, sometimes front-end, etc. Micro-electronics is a wide field and not a job description as such. Analog guys do analog design. Digital engineer's main priority is advanced node, power, speed, cost; while analog designers have different priority. Due to the sensitivity of their design (remember they don't deal with just 5V and 0V like digital designer - they need a proper 3V if they want a 3V, which for digital designer is a 5V), their priority is mainly to do proper circuit design and layout for a definitive behavior after fabrication. So, they don't deal with advanced technology rather a matured technology (proven old one). Their challenge is bandwidth, noise, functionality, gain, slew rate, etc. Some analog design include A/D or D/A converter, Op-amps, Oscillators, OTA (project of EE5333), filters, etc.

Knowledge Goes Free - Learn About VLSI

A career in VLSI is very challenging. Not only because this career is too dynamic, but also its very research and knowledge intensive. As Moore's law predict that the integration of devices on a chip area will double every 18 months (note that he had initially predicted it to be 2 years i.e. around 33% less dynamic) it means a lot to a career in VLSI. It tells how quickly the technology changes and how we have to remain updated with the cutting edge technology.
This means the knowledge in this field is not only inevitable but also should be accessible at the right time. Especially, the knowledge related to pioneering technology and on-going research (generally available at industry research labs or classrooms of premiere universities) should get to the market quickly for techies to access and implement it. This blog has an aim to spread awareness and knowledge for the same cause and with this post we are a step ahead.
There are some open course ware thats free for every one to access. So, this knowledge is free and its on us to make proper use of it. Moreover, they are from some of the best institute around the world whose link is provided here:
1. Free video lectures and animations on all subjects Huge Collection. Text materials and videos on all Engineering and Medical Sciences.
2. Joint venture by IIT's and IISc
3. MIT Open Course Text materials, video lectures on all subjects
4. MIT world Video lectures
5. MIT lecture Browser browse video lectures on all topics
6. World Lecture Hall you can find any course here, where ever it is

7. UC Berkeley Course Above link contains webcasts of courses taught at University of California Berkeley. They are categorized under various semesters(top right corner).
Other Useful Search Engines:
1. Google Book Search Search the all books.

2. Google Code Search searches public source code

3. Google Scholar Search searches all the Scholar papers.

4. Educational Special Search Engine searches all sites for e-books, study materials, video lectures, animations, including Google videos, Yahoo videos, you tube, Google code search, Scholar, Book search.

There are some other links that relates to other different areas too. However, its not published here as its out of context. Please mention it in the comments if you need any of those links. So, please make use of these free knowledge sites and make proper use of it. Happy browsing.

Beyond immersion lithography

- Source: EDN Asia Newsletter, By: Kirtimaya Varma, Date: 01, Oct, 2008

While designers move toward 32nm, two reports from IMEC should be of special interest for them. The first is the end of the road for immersion lithography. This is rather disappointing, because high-index immersion lithography using non-water fluids between the optical lens and the wafer was designed to push 193nm immersion lithography toward the 32nm node. Its elimination from the race for the next-generation lithography tools has not come suddenly. Designers had found that in deep nanometrics immersion lithography was behind the roadmap. But now it is confirmed that this lithography has reached its limits.

LITHOGRAPHY OPTIONS: The two lithography options being developed for 32nm and possibly beyond are double patterning and EUV. EUV technology is still years away and is expected to mature only in the middle of the next decade. This leaves double patterning to bridge the gap between immersion and EUV lithographies. Most designers agree that double patterning will be the best option for the 32nm half pitch during early next decade, and some hope that EUV will take over at 22nm half pitch. However, there is no consensus on which of the several double patterning approaches using the existing 193nm immersion toolset will prevail. For one thing, all the present double patterning methods entail huge extra costs because of extra process steps involved. IMEC is conducting a study on various double patterning methods with a view to assess the feasibility and cost-effectiveness of various processes and to validate the most promising ones in terms of cost, implementation, and process controllability, and is developing alternate process flows that reduces the cost-of-ownership by eliminating the intermediate etch step and replacing it with a process step in the litho track. The method IMEC has used to eliminate the extra etch step is through freezing the resist after the first exposure. The freezing material, developed by JSR Corporation and compatible with the lithography hardware, prevents the resist from expanding or contracting, so that when the second resist layer is added, the two do not interact. Besides, the freezing material changes the properties of the first resist layer to make it non-soluble in the second resist layer solvent. IMEC is developing this technique in collaboration with resist supplier and is working on improvements of the process conditions, process window, line-edge roughness, overlay, defectivity, and etch performance. With EUV lithography still far away, it is not known how will EUV impact the cost of a design? Today no known EUV radiation source produces sufficient power. With costs going through the roof, some designers are wary of being too optimistic about EUV and believe that double patterning will not stop at 32nm and will extend to nodes beyond. In this connection it is important to note that IMEC has completed the site acceptance tests for ASMLs Alpha-Demo EUV tool that has successfully patterned the contact level of a 32nm SRAM cell using EUV.

DIELECTRIC BREAKTHROUGH: Yet another important announcement IMEC made is its progress on simplified high-K/metal gate process for 32nm node. K has been a matter of concern ever since designs reached 90nm. It is too early to say whether a final solution has emerged, but IMEC reports improved performance for its planar CMOS using hafnium-based high-K dielectrics and tantalum-based metal gates for the 32nm CMOS node. IMEC has simplified its high-K/metal gate process by decreasing the number of process steps from 15 to 9.

IMEC also claims to have simplified the process complexity from dual-metal dual-dielectric to single-metal dual-dielectric by using soft-mask processes and wet removal chemistry. The process reduces the complexity by 40 percent or 6 steps compared to dual-metal dual-dielectric, while allowing simpler gate-etch profile control and offering better prospects for scaling. IMEC works with its core 32nm CMOS partners, including Infineon, Qimonda, Intel, Micron, NXP, Panasonic, Samsung, STMicro, TI, TSMC , Elpida and Hynix.

Link: http://www.ednasia.com/article-21907-Asia.html

Sun-tracking device wins student prize

- Source: IEEE Students, October Newsletter, By: David Chandler, MIT News Office, Date: September 19, 2008

A team of three students who designed a system that could allow solar power panels to track the sun without motors or control systems won top honors Thursday -- and a check for $10,000 -- in the finals of a competition aimed at developing innovative energy technologies.
This was the second annual MADMEC -- which stands for Making And Designing Materials Engineering Contest -- and it offered students six categories of engineering challenges related to producing innovative solutions for energy-related problems in the developing world. The contest is co-sponsored by MIT's Department of Materials Science and Engineering (DMSE) and by corporate sponsors Dow Chemical, Saint Gobain and General Motors.
The competition began last spring, and all four of the teams that made it to the finals won prizes, ranging from the $10,000 top award to $1,000 for the fourth-place finishers.
The winning team, called Heliotrope, chose to imitate the way plants track the sun across the sky, by using the difference in temperature between shaded and sunny areas to change the properties of the material supporting solar photovoltaic cells. The system, once built, is completely passive, requiring no power source or electronics to control the movement. Solar cells that track the angle of the sun can be 38 percent more efficient at generating power than those that are mounted in a fixed position, explained team member George Whitfield, a graduate student in DMSE.
The team explored several different variations of the proposed system, using various materials including polymers and bimetallic strips. The system that shows the most promise, they said, mounts solar panels at the top of a curved arch made of a pair of metals such as aluminum and steel, which should be durable enough to withstand the elements with little or no maintenance.
"We wanted to show this concept in action," Whitfield explained as he demonstrated a scale model of the arch by shining a spotlight to warm up one side and cause the arch to bend, tilting the solar panel toward the light. "Our prototypes are cheaper than existing systems" for tracking the sun, he said, and could be built from materials that are readily available in developing nations.
The second-place winner was a team that worked on a way to make inexpensive coatings for windows that would block infrared light, thus allowing daylight through while blocking the sun's heat to reduce the need for air conditioning. Third place went for simple wind generators that could be placed alongside a road to produce electricity from the movement of passing cars. And the fourth prize went to a simple attachment for a bicycle that could allow it to generate electricity to charge batteries, such as those used in the One Laptop Per Child computers.
"I was very impressed with all the entries," said Ned Thomas, DMSE head and Morris Cohen Professor of Materials Science and Engineering. The department will definitely plan on holding another MADMEC competition starting next spring, he said.

Link: http://web.mit.edu/newsoffice/2008/madmec-0919.html

Novaled Achieves CMOS Logic Technology Breakthrough

- Source: IEEE Circuits, September Newsletter

Making n- and p-type organic thin-film transistors from the same organic semiconductor material could benefit lighting and display technology.
Organic CMOS transistors are attractive for applications where classical silicon-based systems are too expensive. To date most developments in organic CMOS devices are based on pentacene, which usually allows for p-type transistors only, so organic thin-film transistors (OTFTs) have had to use two different organic semiconductors as active layers in order to show n- and p-type behaviour. Novaled has now demonstrated that both n-type and p-type OTFTs can be made from only one active material.
"It is well known that using doped transport layers in OLEDs reduces the driving voltage, increases lifetime and boosts power efficiency," Anke Lemke of Novaled told optics.org. "Now we have shown that introducing redox dopants into OTFTs can change the type of majority carrier. The performance of p-type pentacene OTFTs can be improved by using p-dopants, while introducing n-dopants can change the OTFT from p- to n-type."
This enables the use of "CMOS logic" in organic electronics applications, circuit designs based on n- and p-type transistors featuring low static power dissipation compared to logic circuits using only one type of transistor. Both the performance and the manufacturability of OTFT circuits could be improved by this breakthrough.
"The complementary logic-OTFTs could be used in the lighting and display markets, but also in other sectors such as organic RFIDs," said Lemke. "In the display field, possible applications are backplane driving circuits for active matrix displays."
Introducing dopants into existing organic transistor technologies seems straightforward, but Lemke pointed out that the processing compatibility appears to be even more important with OTFTs than with OLEDs. "Our results so far are proof-of-concept, and we are now starting to transfer our approach to industrial processes. The number of commercially available organic electronic devices is still small, but as they become more widely available we are optimistic that our technology can be introduced commercially in the medium-term."
• Novaled and Vitex have announced a co-operation on OLED thin-film encapsulation, intending to combine the advantages of the Barix thin-film technology developed by Vitex and Novaled's doping technology and produce ultrathin highly efficient OLEDs.
"We intend to integrate Vitex barrier technology into Novaled's OLED prototypes and development programme, and offer a more complete set of OLED component expertise," commented Novaled's Lemke.
Novaled intends to begin offering thin OLED lighting prototype products incorporating the combined technology to lighting companies starting in 2009.

Creating a purer breed of semiconductors

- Source: IEEE Circuits, September Newsletter, By: Sylvie Barak, The Inquirer

FANS OF ELECTRON mobility research rejoice! Boffins at Germany’s Physikalisch Technische Bundesanstalt (PTB) have come up with a brand spanking new high-vacuum semiconductor crystal generation process which purports to produce crystals five times purer than all previous known epitaxy systems.
PTB’s new system apparently relies on an innovative molecular beam epitaxy system, with GaAs (gallium-arsenide) and AlGaAs (aluminum-gallium-arsenide) semiconductor heterostructures forming a base. These are then evaporated in a vacuum and laid down in atomic layers, only a few nanometers thin. These then form an electron layer within the crystals, called a two-dimensional electron gas.
Mobility of electrons depends quite significantly on lowering the amount of impurities, so, to mop up the nasty stuff, the boffins have added special cooling panels to suck up any unwanted waste.
To generate the crystals themselves, a special ultrahigh vacuum is used. At 15 orders of magnitude beneath standard atmospheric pressure, you could say, it sucks. Big time. It is also, by no means, an easy feat and requires multiple stages of vacuum creation, starting with partial vacuums and moving up.
Once the vacuum has been formed, the molecular-beam epitaxy gets going, allowing the incredibly pure crystals to form using the aforementioned layering system.
All this, ultimately, leads to a much purer form of semiconductor, which is good news for Chipzilla and Moore’s Law advocates, as well as to those looking into things like quantum Hall resistance metrology and new thinking on electrical current as a function of frequency and electron charge.
Exciting stuff indeed.